PURPOSE: To attain the operation in response to various bus connection forms by generating a clock in response to a round trip delay between a master station and a slave station.
CONSTITUTION: A comparator circuit 14 judges that in which timing range generated by a timing generating circuit 13 a received frame phase is to be included thereby determining the round trip delay time. The delay amount is used to delay the transmission frame phase from a transmission frame phase delay circuit 12, and a selection circuit 16 selects an optimum signal among some signals being the result of delaying the signal of the transmission frame phase from a transmission frame phase delay circuit 12 or some signals being the result of delaying signals of the received frame phase outputted from a reception frame phase delay circuit 15 and uses the result as a reset signal, which resets a clock generating circuit 17 thereby switching the clock. Thus, the clock switched optimizingly is used as a data read clock. Then the titled circuit is applicable to various bus forms.
KOMINE HIROAKI
SOEJIMA TETSUO
MURANO KAZUO
OKUMURA YASUYUKI
NIPPON TELEGRAPH & TELEPHONE
| JPS6093835A | 1985-05-25 | |||
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