Title:
PIN GRID ARRAY
Document Type and Number:
Japanese Patent JPS6240749
Kind Code:
A
Abstract:
PURPOSE: To reduce the thickness and the cost of a pin grid array by using a circuit board and sealingly molding the board integrally with pins and a heat sink with a mold.
CONSTITUTION: The heads of stepped pins 2 are engaged with through holes 7 of a circuit board 1, the pins 2 are calked with the heads 2b of the pins 2 to be secured to the board 1, and a wiring pattern and the pins 2 are simultaneously electrically connected. The board 1 is disposed in a cavity 17 of a lower mold 15, a heat sink 3 is set to coat the hole 5 of the board 1, an upper mold 18 is then moved down to close the molds, heat resistant resin is injected to the cavity 17, sealed and molded to be manufactured.
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Inventors:
KONISHI AKIRA
WAKANO TERUO
WAKANO TERUO
Application Number:
JP18090185A
Publication Date:
February 21, 1987
Filing Date:
August 16, 1985
Export Citation:
Assignee:
DAI ICHI SEIKO CO LTD
International Classes:
H01L23/12; H01L23/28; H01L23/48; H01L23/50; (IPC1-7): H01L23/12; H01L23/28; H01L23/48
Attorney, Agent or Firm:
Aoyama