To stably restart a voltage-controlled oscillator when its oscillation is stopped in a PLL circuit using combinedly the voltage controlled oscillator having an oscillation stopping area and a frequency divider outputting a fixed frequency at the time of an input non-signal called as a self-exiting oscillation, and to make a device small in size and low in price.

A computer circuit 21 receiving an unlock signal outputted from a phase comparator 14 turns the frequency dividing rate 1/N of the frequency divider 12 to be 1/N' and turns the output self-exciting oscillation frequency to be fosc to make (f osc/N')<(the minimum value/N of f vco), thereby a PLL circuit works as if an oscillation frequency is lowered and the comparator 14 generates such a phase error voltage as elevates the output oscillation frequency f vco of the voltage controlled oscillator 11. Since the PLL circuit works in the direction of raising the oscillation frequency of the voltage controlled oscillator, the stoppage of oscillation can be finished.