Title:
PLL CIRCUIT
Document Type and Number:
Japanese Patent JP2004221962
Kind Code:
A
Abstract:
To reduce jitters generated in an output clock as much as possible when a PLL circuit formed on a semiconductor chip is used as a clock multiplication circuit.
A power supply line connected to the respective circuit blocks of a reference oscillator, a phase comparator, a charge pump circuit, a frequency divider and an output buffer is separated from a power supply line connected to a voltage controlled oscillator.
Inventors:
KANZAKI MINORU
Application Number:
JP2003007222A
Publication Date:
August 05, 2004
Filing Date:
January 15, 2003
Export Citation:
Assignee:
SEIKO EPSON CORP
International Classes:
H01L27/04; H01L21/822; H03L7/08; (IPC1-7): H03L7/08; H01L21/822; H01L27/04
Attorney, Agent or Firm:
Masahiko Ueyanagi
Fujitsuna Hideyoshi
Osamu Suzawa
Fujitsuna Hideyoshi
Osamu Suzawa