Title:
PLL CIRCUIT
Document Type and Number:
Japanese Patent JP3758186
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a PLL circuit capable of realizing application of an accurate phase offset by providing an offset current application section into a charge pump circuit.
SOLUTION: In the PLL circuit provided with: a voltage-controlled oscillator (40) the frequency of the output clock of which is controlled by an input voltage; a frequency divider (50) for dividing an output signal of the voltage-controlled oscillator; a phase comparator (10) for comparing a phase of an output signal of the frequency divider with a phase of a reference signal; a charge pump circuit (20a) driven by an output signal of the phase comparator; and a loop filter (30) for integrating an output of the charge pump circuit, and controlling the frequency of the voltage-controlled oscillator with a voltage stored in the loop filter, the charge pump circuit is provided with a means for generating an offset current to change the phase of the output clock.
Inventors:
Yoshinobu Sugihara
Horiuchi Hitoshi
Horiuchi Hitoshi
Application Number:
JP2002148974A
Publication Date:
March 22, 2006
Filing Date:
May 23, 2002
Export Citation:
Assignee:
Yokogawa Electric Corporation
International Classes:
H03L7/093; (IPC1-7): H03L7/093
Domestic Patent References:
| JP2230820A | ||||
| JP11191270A | ||||
| JP1128621A | ||||
| JP5347544A |
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