PURPOSE: To improve operating frequency by devising the PLL circuit such that a pulse width of a preset signal generated by a preset signal generating circuit is expanded.

CONSTITUTION: A prescaler 7 having two frequency divider ratios and a counter 8 controlled based on an output signal from the prescaler T and a preset signal generating circuit are provided in a loop of the PLL circuit. The preset signal generating circuit consists of FFs 18, 22, an output signal from the prescaler 7 is used as a clock signal and an output signal from the counter 8 is used as a data input. Thus, the output signal from the counter 8 is used as an output signal of the preset signal generating circuit over one period of the signal corresponding to the clock. As a result, the pulse width of the preset signal is expanded. Thus, the operating frequency is improved and malfunction at a high frequency is reduced.