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Title:
PLL SYNTHESIZER
Document Type and Number:
Japanese Patent JP2012044545
Kind Code:
A
Abstract:

To reduce a capacitance value of a capacitor for a temperature-compensation loop filter.

A PLL synthesizer comprises: a phase comparator PD; a loop filter LF; and a voltage-controlled oscillator VCO. In addition, as a temperature-compensation loop, the PLL synthesizer comprises: a comparator CMP that outputs a comparison signal 30 when a frequency control voltage goes out of a control voltage range; a digital filter DF that integrates the comparison signal 30 to generate an M-bit first digital signal 32; ΣΔ modulators 12 and 10 that input the first digital signal 32 and generate a second digital signal 34 corresponding to the first digital signal 32 as an N-bit signal (where N is smaller than M); a temperature-compensation charge pump CPt that converts the second digital signal 34 to a current signal 36; and a temperature-compensation loop filter TF that converts the current signal 36 to a temperature-compensation control voltage. The voltage-controlled oscillator VCO controls a frequency of an output clock CKout based on the temperature-compensation control voltage ft.


Inventors:
CHAIVIPAS WINE
MARUTANI MASAZUMI
YAMAZAKI DAISUKE
Application Number:
JP2010185363A
Publication Date:
March 01, 2012
Filing Date:
August 20, 2010
Export Citation:
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Assignee:
FUJITSU LTD
FUJITSU SEMICONDUCTOR LTD
International Classes:
H03L7/093; H03L1/02
Domestic Patent References:
JP2009284221A2009-12-03
JP2010081513A2010-04-08
JPH06334526A1994-12-02
JPH0496515A1992-03-27
JP2005260446A2005-09-22
JP2000243043A2000-09-08
JP2002124880A2002-04-26
JPH11214990A1999-08-06
JPH11214988A1999-08-06
JP2009182698A2009-08-13
Foreign References:
US7133485B12006-11-07
Attorney, Agent or Firm:
Kenji Doi
Hayashi Tsunetoku



 
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