Title:
PLL SYNTHESIZING OSCILLATOR
Document Type and Number:
Japanese Patent JP3797791
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce the influences of noise floors of a divider and of a phase comparator and to decease phase noises by extracting a frequency component at an intermediate stage of an output frequency divider to compare the frequency component with a finally divided frequency and performing phase comparison with the frequency of a reference signal based on the higher frequency determined by the above comparisons.
SOLUTION: A signal inputted to a modulus pre-scaler 4 is controlled by an M-CNT and then divided with a dividing ratio switched to 16 or 17 ratio. The divided signal is inputted to a variable divider 5 to undergo 4-division, 2-division, 2-division and 2-division at the 1st, 2nd, 3rd and 4th stages respectively and finally undergoes a 32-division via a divider 5. A signal of 20 MHz, i.e., the output that has undergone the 4-division at the 1st stage of the divider 5, is extracted and inputted to a phase comparator 7. Thus, phase comparison is enabled with 20 MHz component of a reference signal and accordingly margins are secured to the noise floors of the pre-scaler 4, each divider, the comparator 7, etc.
Inventors:
Ryuzo Yamamoto
Application Number:
JP12896798A
Publication Date:
July 19, 2006
Filing Date:
May 12, 1998
Export Citation:
Assignee:
New Japan Radio Co., Ltd.
International Classes:
H03L7/08; H03L7/18; H03L7/197; (IPC1-7): H03L7/197; H03L7/08
Domestic Patent References:
| JP63296522A | ||||
| JP1188026A | ||||
| JP6152393A |