PLOTTING SYSTEM AND SEMICONDUCTOR INTEGRATED CIRCUIT FOR PERFORMING PLOTTING ARITHMETIC OPERATION

Title:

PLOTTING SYSTEM AND SEMICONDUCTOR INTEGRATED CIRCUIT FOR PERFORMING PLOTTING ARITHMETIC OPERATION

Document Type and Number:

Japanese Patent JP2001195230

Kind Code:

A

Abstract:

To reduce the storage capacity of a frame memory to be used for a plotting system.

This plotting system is provided with a plotting arithmetic circuit 2 for performing an arithmetic operating for generating plural pixel data corresponding to plural pixels constituting one screen, first memory 3 for receiving and storing the plural generated pixel data, and a second memory 5 for receiving and storing the plural pixel data from the first memory, and for outputting the stored data and displaying a picture at a display device. Each pixel data includes three color information indicating the red color, green color, and blue color of the pixels and alpha value information indicating the transparency of the pixels. When the data are transferred from the first memory to the second memory, the value information among each pixel data is removed so that data amounts to be stored in the second memory can be reduced.

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Inventors:

MORIWAKI SHOHEI
AZEKAWA YOSHIIKU
CHIBA OSAMU
SHIMAKAWA KAZUHIRO

Application Number:

JP2000005417A

Publication Date:

July 19, 2001

Filing Date:

January 14, 2000

Export Citation:

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Assignee:

MITSUBISHI ELECTRIC CORP
MITSUBISHI DENKI SYS LSI DES

International Classes:

G06F3/153; G06T1/20; G06T1/60; G06T3/00; G06T11/00; G09G5/00; G09G5/02; G09G5/36; G09G5/393; H01L21/822; H01L27/04; (IPC1-7): G06F3/153; G06T1/60; G06T1/00; G06T11/00; G09G5/02; H01L27/04; H01L21/822

Attorney, Agent or Firm:

Kaneo Miyata (1 person outside)

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