Title:
POTENTIAL TAKE-OUT STRUCTURE FOR CHIP AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JP3299715
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a potential take-out structure for a chip in which the size can be reduced while avoiding electrical troubles.
SOLUTION: A pressure sensor 10 comprises an extending part 42 formed on a lower glass 40, and a signal take-out part 50 deposited from the upper surface 42A of the extending part 42 to the upper surface 30B of a lower glass 30. The signal take-out part 50 does not touch a circuit board when the pressure sensor 10 is mounted thereon and electrical troubles, e.g. picking up noise from the signal take-out part 50, can be avoided. Since the signal take-out part 50 is formed of a deposition film, the structure for taking out a potential from a diaphragm does not require a significant space and the size of the pressure sensor 10 can be reduced.
Inventors:
Yukimitsu Sekimori
Seiichi Yokoyama
Fumio Kaise
Seiichi Yokoyama
Fumio Kaise
Application Number:
JP8868298A
Publication Date:
July 08, 2002
Filing Date:
April 01, 1998
Export Citation:
Assignee:
Nagano Keiki Co., Ltd.
International Classes:
G01L9/12; G01L9/00; G01L13/06; G01P15/125; H01L29/84; (IPC1-7): G01L9/12; G01L13/06; G01P15/125; H01L29/84
Domestic Patent References:
| JP1082709A | ||||
| JP2134570A | ||||
| JP9210824A |
Attorney, Agent or Firm:
Minoru Kinoshita (1 person outside)