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Title:
POWER CONSUMPTION REDUCING SYSTEM IN DRAM
Document Type and Number:
Japanese Patent JPH07282580
Kind Code:
A
Abstract:

PURPOSE: To reduce the power consumption of a DRAM by decreasing the number of bits being in a level 1 of data to be stored in the DRAM.

CONSTITUTION: At the time of writing data in a DRAM 5, a data deciding part 2 decides whether the number of bits being in a level 1 of data inputted to data busses 1 exceeds the majority of the number of all bits of input data or not to output the result to a selection part 4 and the DRAM 5. The selection part 4 selects inverted data from a data inverting part 3 when the decision result exceeds the majority and selects input data from the data busses 1 when the result is less than the majority to output them to the DRAW 5. At the time of reading data from the DRAM 5, the selection part 4 selects the inverted data from the data inverting part 3 when the decision result exceeds the majority and selects input data from the DRAM 5 when the result is less than the majority to output them to the data busses 1.


Inventors:
INOUE MASAHIRO
Application Number:
JP7368894A
Publication Date:
October 27, 1995
Filing Date:
April 13, 1994
Export Citation:
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Assignee:
NEC COMMUNICATION SYST
International Classes:
G11C11/407; (IPC1-7): G11C11/407
Domestic Patent References:
JPH0240194A1990-02-08
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)