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Title:
POWER CONVERTER IN SET PARALLEL CONFIGURATION AND ELEVATOR SYSTEM USING THE SAME
Document Type and Number:
Japanese Patent JP2009033909
Kind Code:
A
Abstract:

To accurately know abnormality information, cutoff operation information, and time-series order for the information even a power converter in a set parallel configuration in which a plurality of arithmetic processors are used.

The power converter in the set parallel configuration includes: PWM rectifiers 3A, 3B and inverters 4A, 4B, in which serial connections of the rectifier 3A and the inverter 4A and the rectifier 3B and the inverter 4B are connected in parallel; a PWM rectifier side arithmetic processor 6 which performs control calculation of the PWM rectifiers; and an inverter side arithmetic processor 7 which performs control calculation of the inverters. The PWM rectifier side arithmetic processor 6 which detects that an abnormality occurs in the PWM rectifiers and the inverter side arithmetic processor 7 which detects that an abnormality occurs in the inverters are provided to send signals to each other when an abnormality is detected in either of the PWM rectifier side arithmetic processor 6 or the inverter side arithmetic processor 7.


Inventors:
AYANO HIDEKI
INABA HIROMI
ONUMA NAOTO
MORI KAZUHISA
HIRUTA KIYOHARU
SAKOTA TOMOJI
MITA FUMIAKI
HOTATE HISAFUMI
Application Number:
JP2007196873A
Publication Date:
February 12, 2009
Filing Date:
July 30, 2007
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H02M7/493; B66B1/30; B66B1/34; B66B5/00; H02M7/48; H02P21/00; H02P25/22; H02P27/04; H02P27/06; H02P27/08
Domestic Patent References:
JP2002302351A2002-10-18
JP2000134947A2000-05-12
JPH11341823A1999-12-10
JPH05260793A1993-10-08
JP2004210507A2004-07-29
JPH0323180A1991-01-31
JPH11209011A1999-08-03
JPH07255179A1995-10-03
JP2006062799A2006-03-09
Attorney, Agent or Firm:
Manabu Inoue
Yuji Toda