Title:
POWER FACTOR IMPROVEMENT CIRCUIT
Document Type and Number:
Japanese Patent JP3493285
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To easily and completely prevent overshoot and undershoot during starting, without forming a dedicated clamp circuit or the like, even if the responsiveness of output voltage control at the time of normal operation is delayed for power factor improvement.
SOLUTION: The output DC voltage of a DC/DC converter is inputted via an input resistor, and an error between the voltage and a prescribed reference voltage is detected. To an error amplifier 14 formed with an integrating circuit of a time constant determined by a capacitor C2 connected to a return circuit and the input resistor R3, a response improvement circuit 13 is formed, which is connected to diodes D3, D2 for improving the responsiveness with the time constant of an integrating circuit decreased by the short-circuiting of the input resistor, when transient response voltage generated at an input resistor R3 as an oscillatory waveform with the reference voltage centered exceeds a prescribed voltage which is positive or negative in a transient response condition of the output DC voltage due to power input.
Inventors:
Masaharu Maesaka
Application Number:
JP22592497A
Publication Date:
February 03, 2004
Filing Date:
August 22, 1997
Export Citation:
Assignee:
Cosel Co., Ltd.
International Classes:
H02J3/01; H02J3/18; H02M1/12; H02M3/155; (IPC1-7): H02M3/155; H02J3/01; H02J3/18; H02M1/12
Domestic Patent References:
| JP5275186A | ||||
| JP1165923A | ||||
| JP9205367A | ||||
| JP5191204A |
Attorney, Agent or Firm:
Susumu Takeuchi (1 person outside)