To reduce a standby power of a simple and inexpensive power factor improving circuit by conforming to a new standard LEVEL V of "ENERGY STAR (R)" to improve a power factor.
A power factor improving circuit boosts a rectified voltage obtained by rectifying an AC input voltage from an AC power supply Vin by turning on/off a switching element Q1 and improves the power factor to output a boost output voltage to a DC-DC converter circuit driven by a first pulse signal. The power factor improving circuit has: a delay circuit 12 for inputting a first pulse signal of pulse width corresponding to an output voltage of the DC-DC converter circuit, generating a delay pulse signal having a pulse width corresponding to the rectified voltage when an on pulse of the first pulse signal occurs, and compositing the first pulse signal and the delay pulse signal from the delay circuit to generate a second pulse signal; a switching element Q1 driven by the second pulse signal generated by the delay circuit; a gate ON/OFF circuit 13; and a detection circuit 11 for detecting the rectified voltage.
UCHIDA AKIHIRO
JP2000350460A | 2000-12-15 | |||
JPH07135774A | 1995-05-23 | |||
JPH0787732A | 1995-03-31 | |||
JP2003338552A | 2003-11-28 | |||
JP2000350460A | 2000-12-15 |