Title:
POWER FET CONTROL CIRCUIT
Document Type and Number:
Japanese Patent JP3249239
Kind Code:
B2
Abstract:
PURPOSE: To guarantee a function of a power FET control circuit even when the circuit is different from a ground potential of a load by applying a voltage lower than a supply voltage to a depletion FET gate connected between a gate and a source of a power FET via a controllable switch.
CONSTITUTION: When a controllable switch 12 is turned on, an input voltage Uin is applied to a gate terminal of an FET 5. The input voltage Uin is lowered than a service voltage +UBB. Thus, a current flows to a terminal 13 from a terminal 3 via resistances 6 and 20 and the switch 12. The resistances 6 and 20 are selected so that the conduction of the FET 5 is controlled and a depletion transistor TR 16 is obstructed. The current also flows to a base terminal of a TR 8 passing through a resistance 14 on the other hand and via a drain-source section of the FET 5. In such a constitution, the conduction of the TR 8 is controlled, the current flows to a gate terminal of an FET 1 via a diode 9 and resistances 17 and 19 and the gate-source capacity is charged for conducting the FET 1.
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Inventors:
Jenne Chang Yi
Application Number:
JP13439693A
Publication Date:
January 21, 2002
Filing Date:
June 04, 1993
Export Citation:
Assignee:
Siemens Aktiengesellschaft
International Classes:
H02H7/20; H02M1/08; H02M7/12; H02M7/25; H03K17/06; H03K17/08; H03K17/687; (IPC1-7): H03K17/08; H03K17/687
Domestic Patent References:
| JP62219712A | ||||
| JP2182021A |
Attorney, Agent or Firm:
Toshio Yano (2 outside)