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Patent Searching and Data


Title:
PREPARING INTERPOLATION TYPE MOS SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS5574175
Kind Code:
A
Abstract:

PURPOSE: To provide a high degree of intergration by a method wherein opening are made on the SiO2 film on p and n-type diffusion layers and, after injection of the same type impurity ions, the openings are stacked with semiconductor layer and wiring layer.

CONSTITUTION: In a CMOS device, openings are made on the SiO2 film on an Si substrate in which source and drain layers have been formed on the p-type and n- type areas. The openings expose p and n-type layers, on which the same type impurity ions are injected respectively to form diffusion layers 5a, 6a. Then, the openings are provided with adition-free polycrystalline Si 11 and Al wiring 1 in double layers. Although Si diffuses into Al, the Si is supplied from the Si layer 11 and therefore the diffusion layers 5, 6 are completely unaffected, thereby providing a good pn-junction property. Even when the openings are shifted from the layers 5, 6, the ion injection layers 5a, 6a formed on the substrate 3 at the locations of the openings prevent short-circuit failures. As such, the process prevents alloy spike, and provides shallow diffusion layers and compactly sized elements.


Inventors:
KAWAMATA IKUO
Application Number:
JP14760578A
Publication Date:
June 04, 1980
Filing Date:
November 29, 1978
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L29/08; H01L21/28; H01L21/8238; H01L27/092; H01L29/78; (IPC1-7): H01L27/08; H01L29/08; H01L29/62; H01L29/78
Domestic Patent References:
JPS51137384A1976-11-27
JPS51134566A1976-11-22
JPS51116675A1976-10-14