PURPOSE: To optimize the processing speed of a processor in accordance with the processing contents by setting variably the count value of a shift register in terms of software based on the external data.

CONSTITUTION: A shift register 1 is provided to count the wait number of a CPU with a shift action carried out by a clock together with a wait control part 2 which sets the count value, i.e., the count number of the register 1, a data register 3 which fetches the wait number set by the part 2 via a system data bus 51, and a decoder 4 which selects the register 3 based on the address data on a system address bus 52. Then plural sets of registers 1, parts 2 and registers 3 are used as necessary, and each of these sets is selected by the decoder 4. Then the wait number of the processors like the CPU, etc., can be optionally and variably set in accordance with the processing contents, etc.