PURPOSE: To improve the performance of a system at the time of operating a matrix by connecting respective chips to an off-chip memory area by an (m)-bit width route and selectively constituting the route as a 1-bit route or the (m)-bit route.

CONSTITUTION: Plural sub arrays S1-S4 are provided, the respective sub arrays S1-S4 are provided with the (n) pieces of processor elements PEs, the respective processor elements PEs are connected to a local storage device provided with an on-chip memory and the respective chips are connected to the off-chip memory area by the (m)-bit width route {(m) is an integer > 1}. The route is selectively constituted as the 1-bit route connected to the respective (m) processor elements PEs or the (m)-bit width route composed so as to communicate the complete (m)-bit word of memory data between the off-chip memory area and the respective processor elements PEs. Thus, the elements of the matrix stored in an off-chip memory are accessed at a high speed.