Title:
PROCESSOR SYSTEM, SEMICONDUCTOR INSPECTION SYSTEM, AND PROGRAM
Document Type and Number:
Japanese Patent JP2023103539
Kind Code:
A
Abstract:
To provide a technique capable of quantitatively grasping a change in a three-dimensional shape including a cross-sectional shape of a pattern in a wafer plane or between wafers non-destructively before performing cross-sectional observation.SOLUTION: A processor system of a semiconductor inspection system performs the steps of: acquiring a captured image by an electron microscope (SEM) about a sample (S102); calculating a first feature amount corresponding to each of a plurality of sites in a reference region defined on a sample surface about the reference region from the captured image (S103A); calculating a first statistic from the first feature amount in the plurality of sites (S103B); calculating a second feature amount corresponding to each of one or a plurality of sites in an evaluation region about each of a plurality of evaluation regions made to correspond to a reference region and defined as a dot or a region on the sample surface as a feature amount having the same kind as the first feature amount from the captured image (S104A); and obtaining a second feature amount after conversion by converting the second feature amount by the first statistic (S105).SELECTED DRAWING: Figure 6
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Inventors:
YASUI KENJI
OSAKI MAYUKA
NAMAI HITOSHI
KOJIMA TAKEKI
NAGATOMO WATARU
IKODA MASAMI
KIMURA MAKI
OSAKI MAYUKA
NAMAI HITOSHI
KOJIMA TAKEKI
NAGATOMO WATARU
IKODA MASAMI
KIMURA MAKI
Application Number:
JP2022004104A
Publication Date:
July 27, 2023
Filing Date:
January 14, 2022
Export Citation:
Assignee:
HITACHI HIGH TECH CORP
International Classes:
G01B15/00; H01L21/66; G01B15/04
Attorney, Agent or Firm:
Patent Attorney Tsutsui International Patent Office
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