Title:
正規化カウントを判定するプロセッサ及び方法
Document Type and Number:
Japanese Patent JP2011509491
Kind Code:
A
Abstract:
In a particular embodiment, a method is disclosed that includes receiving an operand to be normalized at a normalization logic circuit, where the operand includes a plurality of bits. The method further includes generating a zero output when a value of the operand is equal to zero and, when the value is not equal to zero, generating an output value representing a number that is one less than a count of leading bits of the operand.
Inventors:
Clicibasan, shanker
Pronke, Elitch Jay.
Cordescu, Lucian
Jeng, Mao
Pronke, Elitch Jay.
Cordescu, Lucian
Jeng, Mao
Application Number:
JP2010542362A
Publication Date:
March 24, 2011
Filing Date:
January 09, 2009
Export Citation:
Assignee:
QUALCOMM INCORPORATED
International Classes:
G06F7/00; G06C3/00
Domestic Patent References:
| JPH07319671A | 1995-12-08 | |||
| JPH06236252A | 1994-08-23 | |||
| JPH01185726A | 1989-07-25 | |||
| JPH0480815A | 1992-03-13 | |||
| JP2003216410A | 2003-07-31 |
Attorney, Agent or Firm:
Kurata Masatoshi
Satoshi Kono
Makoto Nakamura
Yoshihiro Fukuhara
Takashi Mine
Toshio Shirane
Sadao Muramatsu
Nobuhisa Nogawa
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Katsumura Hiro
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori
Takuzo Ichihara
Yamashita Gen
Satoshi Kono
Makoto Nakamura
Yoshihiro Fukuhara
Takashi Mine
Toshio Shirane
Sadao Muramatsu
Nobuhisa Nogawa
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Katsumura Hiro
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori
Takuzo Ichihara
Yamashita Gen