To attain the product-sum operation of digital multipliers corresponding to plural analog voltage values by the comparatively small number of capacitance elements by adding bits corresponding to the multipliers of plural data and then weighting the added result in accordance with the weight values of respective bits.
An addition part ADD is connected to a sample and hold part SH to which analog input voltage Vin is inputted, plural analog voltage values stored in the sample and hold part SH are mutually added and the added result is multiplied in a multiplication part MUL. A control signal CTRL1 is inputted from a multiplier control circuit CTRL to the sample and hold part SH and a control signal CTRL2 is inputted to the addition part ADD. Thus the corresponding bits of multipliers of plural data are mutually added at first, and then the added result is weighted in accordance with the weight values of respective bits. When multipliers are circulated, transfer errors can be suppressed.
MOTOHASHI KAZUNORI