To perform the product-sum operations of digital multipliers against plural analog voltage levels via a comparatively small number of capacitance by performing first the addition in each corresponding bit of multipliers of plural data and then performing the weighting to the addition result according to the weight of each bit.

An ADD(addition) part is connected to an SH(sample holding) part, and plural analog voltage levels held at the SH part are added together. Then the multiplication is applied to the addition result at a MUL(multiplication) part. The SH part consists of plural sample holding circuits which are placed in series to each other, and the ADD part consists of plural addition circuits which are placed in parallel to each other. The sample holding circuits output their holding analog voltage in parallel to each other and in number equal to double as much as the number of bits of digital multipliers to be multiplied. Then the addition circuits correspond to the positive and negative multipliers respectively.