PURPOSE: To set a time change characteristic of an attenuation by selecting a frequency of a clock signal inputted to a down-counter.
CONSTITUTION: A switching address generating circuit 6 detects whether or not a count of a count signal 161 of a down-counter 4 reaches a prescribed count. Then a switching address signal 201 to switch sequentially clock signals 121-12M is outputted to a selector 3. A count control circuit 5 stops the operation of the counter 4 when a signal 161 of the counter 4 reaches all 0. The time when an output period of the signal 161 outputted from the counter 4 depends on the frequency of the signals 121-12M inputted to the counter 4. Thus, the attenuation time characteristic of the analog signal 171 is set by selecting the frequency of the signals 121-12M.
JP4435197 | Semiconductor integrated circuit |
JPS58111528 | LOW-PASS FILTER |
JP2896219 | [Title of Invention] Digital-to-analog converter |
MATSUI YASURO
NIPPON ELECTRIC ENG