PURPOSE: To obtain a pulse frequency divider circuit with high accuracy and low power consumption excellent in the degree of freedom of selection of a reference frequency.

CONSTITUTION: A 1st frequency divider circuit 10 is made up of a 50adic counter 11 and a 1920-adic counter 12 and frequency-divides a reference signal (c)of 19.2MHz with a 1st frequency division pulse p1. A 2nd frequency divider circuit 20 is made up of a 164-adic counter 21, a 4096-adic counter 22 whose output initializes the 164-adic counter 21, and an OR circuit 23 ORing an output of the 164-adic counter 21 and an output of the 4096-adic counter 22 to frequency- divide a reference signal (d) with a frequency of 32.768kHz into a 2nd frequency division pulse p2. A correction value output circuit 30 inputs the pulse p2 to generate a correction value (i) for the correction of the error of the pulse p2 and to set the correction value to the 1920-adic counter 12 when the 1st destination circuit 10 is selected from the 2nd frequency divider circuit 20. A selector 2 selects the 1st frequency division pulse p1 or the 2nd frequency division pulse p2 to provide an output of the selected pulse.