PURPOSE: To allow the circuit to be hardly affected by power fluctuation by providing an initial value generating circuit and using an initial value designation signal so as to set an initial value of a 1/n frequency divider circuit and a 1/2 frequency divider circuit.

CONSTITUTION: With the input of a set input signal pulse 22, '2' and '0' or '1' are set to a 1/n frequency divider circuit 1 and a 172 frequency divider circuit 3. The 1/n frequency divider circuit 1 applies 1/5 frequency division to an input signal 21 to be frequency-divided according to a frequency division data and outputs a 1/n frequency division signal 25 in which its high level corresponds to a '3' of the frequency division data and its low level corresponds to a '5' of the frequency division data. A delay circuit 2 delays a leading edge of the 1/n frequency division signal 25 by a set delay time tD2 and outputs a resulting delay signal 23. In this case, since the leading of the 1/n frequency division signal 25 is delayed, the time tD2 is enough to be short. Finally, the 1/2 frequency divider circuit 3 outputs a frequency division output signal 24 changed at the leading edge of the delay signal 23.