PURPOSE: To make a delay time uniform due to a signal line and obtain uniform time resolution by setting signal line load capacitance to which plural delay elements are connected equivalent.

CONSTITUTION: The NOT AND circuit NAND which is a delay element and inverters IN1-IN62 are connected to a ring delay pulse generating circuit 10 in series, and the output of the final-stage inverter IN62 is connected to the NAND. Then the NAND and IN1, and IN1 and IN2 are connected by a signal line A, the IN31 and IN32 are connected by a signal line B1 at a return part, and the IN62 and NAND are connected by a signal line B2. Then the signal lines A, B1, and B2 are equalized in load capacity and length. A pulse selector 20 consisting of 63 DFFs is arranged at the ring-shaped external part encircled with those signal lines and each signal line is minimized in length. Consequently, delay pulses C1-C63 become steep and can be outputted at uniform time intervals.