Title:
PULSE RECEIVER
Document Type and Number:
Japanese Patent JP3113596
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a pulse receiver for which production process of a receiver is simple compared with the traditional technique.
SOLUTION: A pair of common gate amplifiers 7A, 7B are connected between the power source (ECL) voltage rail of 5v and the ECL ground (AGND), and receive a pair of pulse input signals, and output a pair of first pulse signals, and a distortion circuit distorts the first pulse signal, and generates plural second pulse signals with duty cycle with a low logical level interval longer than a high logical level interval. A latch 11 receives and latches plural second output signals from the common gate amplifiers 7A, 7B at a logical level interchangeable with a circuit formed from a CMOS element. A CMOS double-to-single end converter 13 is connected between a VDD voltage rail and the VSS ground, and receives the latched output signal, and an output circuit outputs an output signal from the converter based on the VDD and the ground.
Inventors:
Patrice Gaudition
Application Number:
JP34738896A
Publication Date:
December 04, 2000
Filing Date:
December 26, 1996
Export Citation:
Assignee:
PMC-Sierra Limited
International Classes:
H04B1/26; H03K19/0185; H03K19/094; H03K19/0952; H04B1/16; (IPC1-7): H04B1/16; H03K19/094; H03K19/0952
Attorney, Agent or Firm:
Aoyama Ryo (2 outside people)