Title:
PULSE WIDTH MODULATING CIRCUIT
Document Type and Number:
Japanese Patent JP3487437
Kind Code:
B2
Abstract:
PURPOSE: To output power pulse having waveform faithful to set data by a method wherein two specified modes are changed over on the border, which is the predetermined time in a certain period corresponding to the period of controlling pulse inputted in a delaying means.
CONSTITUTION: Similarly as a decoder 6, a decoder 7 finished the decoding of a pulse width setting data PWD before the arrival of clock pulse CLKP on the final stage of a programmable delay circuit 3. Before the inputting of the clock pulse CLKP in a programmable delay circuit 4, the selection of the output of what number of the stage is set. In the pulse width modulating circuit 1 concerned, the priority is provided in a set input to be inputted in a RS-FF circuit 5 and a reset input so as to output the originally desired pulse waveform even when both set pulses S1 and S2 outputted from the programmable delay circuits 3 and 4 are at the H level. At the same time, the priority of the inputs is made possible to change over in response to the pulse width of an output pulse.
Inventors:
Hideki Yoshida
Daisuke Murakami
Daisuke Murakami
Application Number:
JP36028692A
Publication Date:
January 19, 2004
Filing Date:
December 29, 1992
Export Citation:
Assignee:
ソニー株式会社
International Classes:
B41J2/44; B41J2/385; H03H17/08; H03K7/08; H04N1/036; (IPC1-7): H03K7/08; B41J2/385; B41J2/44; H03H17/08; H04N1/036
Domestic Patent References:
| JP637608A |
Attorney, Agent or Firm:
Keiki Tanabe