To solve a problem in which if a signal of an oscillator is divided by a divider of a PLL synthesizer so as to increase a frequency resolving power, when a divided signal is below the phase noise generated by the divider, the phase noise of the divider becomes dominant and the frequency resolving power is degraded and when the phase noise is suppressed at a low level, the frequency resolving power becomes rough and thus, a transmission signal having a center frequency of a desired frequency difference off-set cannot be generated.
By use of a phase locked loop frequency synthesizer of a fractional-N system for the PLL synthesizer, the phase noise is suppressed at the low level, the frequency resolving power is increased and a degree-of-freedom of a discrete frequency can be increased. Further, by use of an even harmonic frequency synthesis circuit outputting a frequency synthesized with a double-wave of a local signal as a frequency synthesis circuit, suppression of an unwanted wave is facilitated by a band pass filter.
Tadahiko Inaba
Kanako Murakami
Nakatsuru Kazutaka
Next Patent: INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, AND INFORMATION PROCESSING METHOD