To generate random number data which are irregular and hardly predicted and to generate the random number data fast with simple constitution by generating the random number data by making use of bit data sent through an external signal line.

A random-bit generating circuit 110 adds bit data which changes with time according to process contents to be executed by a CPU to respective bit data stored in a 1-bit shift register 111, a 2-bit shift register 115, a 25-bit shift register 122, and a 20-bit shift register 123 constituting what is called a 48-bit M-series random number generating circuit. Namely, the respective bit data A0 to A19 of a 20-bit address signal sent through a system bus, the respective bit data D0 to D15 of a 16-bit data signal, and the respective bit data of 12 bits in total composed of other signals are added respectively. The 3 bytes obtained by the addition, i.e., data D10 to D115, D20 to D215, and D30 to D316 of 48 bits in total are outputted as random number data.