Title:
受信回路
Document Type and Number:
Japanese Patent JP5510297
Kind Code:
B2
Abstract:
A reception circuit includes: a sampling circuit to sample an input data signal based on a clock signal and output a sampled signal; a data interpolation circuit to interpolate the sampled signal based on phase information corresponding to the sampled signal and output an interpolated data signal; an interpolation error decision circuit to output an interpolation error based on the sampled signal and the phase information; a decision/equalization circuit to equalize the interpolated data signal using an equalization coefficient set based on the interpolation error, to check an equalized interpolated data signal and to output a checked signal; and a phase detection circuit to generate the phase information based on at least one of the checked signal and the equalized interpolated data signal and output the phase information to the data interpolation circuit and the interpolation error decision circuit.
Inventors:
Shiba saki takayuki
Application Number:
JP2010271775A
Publication Date:
June 04, 2014
Filing Date:
December 06, 2010
Export Citation:
Assignee:
富士通株式会社
International Classes:
H04L25/03; H04B3/06
Domestic Patent References:
| JP2005108295A |
Other References:
Spurbeck, M., Behrens, R.T.,Interpolated timing recovery for hard disk drive read channels,Communications, 1997. ICC '97 Montreal, Towards the Knowledge Millennium. 1997 IEEE International Conference on,1997年 6月,Volume 3,Pages 1618-1624
Gardner, Floyd M.,Interpolation in digital modems - Part I: Fundamentals,Communications, IEEE Transactions on,1993年 5月,Volume 41, Issue 3,Pages 501-507
Gardner, Floyd M.,Interpolation in digital modems - Part I: Fundamentals,Communications, IEEE Transactions on,1993年 5月,Volume 41, Issue 3,Pages 501-507
Attorney, Agent or Firm:
Takayoshi Kokubun