Title:
RECEIVER, TRANSMITTER AND TRANSMITTER/RECEIVER
Document Type and Number:
Japanese Patent JP3845025
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a receiver, a transmitter and a transmitter/receiver of which the power consumption are more efficiently suppressed than before.
SOLUTION: While data are transferred and stored from an SIO 20 to an RAM 30 by a DMAC 28 in reception, total data length is acquired from among the stored data by a CPU 26. When acquiring the total data length, the CPU 26 calculates the number of times of implementation of transfer to be performed by the DMAC 28, and resets the DMAC 28. When performing transfer the reset number of times of implementation, the DMAC 28 transmits a command to the CPU 26, and when receiving the command, the CPU 26 stops power supply to a radio part 1. Thus, it is possible to supply a power to the radio part 1 not during all slots as before but for the minimum time necessary for reception, thereby reducing power consumption more.
Inventors:
Mitsuhiro Iida
Application Number:
JP2002021920A
Publication Date:
November 15, 2006
Filing Date:
January 30, 2002
Export Citation:
Assignee:
ADC Technology Co., Ltd.
International Classes:
H04L29/08; (IPC1-7): H04L29/08
Domestic Patent References:
| JP2001119438A | ||||
| JP5136846A | ||||
| JP4132368A | ||||
| JP11145939A | ||||
| JP2001268219A |
Attorney, Agent or Firm:
Tsutomu Adachi