Title:
RECEIVING CIRCUIT
Document Type and Number:
Japanese Patent JP3235727
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To facilitate operation response by storing output from a conversion part, supplying a clock signal to a logical circuit and a processing circuit part only when a stored value exceeds a prescribed level, and supplying a clock signal to the logical circuit and the processing circuit part only in the case of receiving a transmission signal.
SOLUTION: When a CP output signal, namely a received signal, repeats 'L', 'H' potentials for a prescribed time and an O carrier signal exceeds a threshold VTH, a gate G1 is turned on. Thus, a clock signal from a transmission circuit is supplied to a logical circuit and a CPU part 200. When the CP output signal runs out, since electric discharge is executed by a time constant decided by a resistor R 21 and a capacitor C20 in an integration circuit, the gate G1 is turned off. Thus, only when the CP output signal is given, a clock signal is given to the logical circuit and the part 200, thereby current consumption can be reduced. In addition, fast response is possible.
Inventors:
Noboru Kanzaki
Yutaka Yoshida
Yutaka Yoshida
Application Number:
JP2000190616A
Publication Date:
December 04, 2001
Filing Date:
September 16, 1993
Export Citation:
Assignee:
Fuji Electric Co., Ltd.
International Classes:
H04L29/00; H04L12/40; (IPC1-7): H04L29/00; H04L12/40
Domestic Patent References:
| JP3192410A | ||||
| JP5955522A | ||||
| JP541709A | ||||
| JP6237253A | ||||
| JP583240A |
Attorney, Agent or Firm:
Iwao Yamaguchi (2 people outside)