Title:
RECONFIGURABLE SEMICONDUCTOR LOGIC CIRCUIT
Document Type and Number:
Japanese Patent JP2020010007
Kind Code:
A
Abstract:
To provide means for realizing large capacity, low cost, and high speed of a logic LSI in the logic LSI formed on a planar pattern, continued even after the limit of Moore's law due to the short channel effect, etc.SOLUTION: By using an even number (2×((number of stacked stages/2)-1)) of logic circuit stacked connection structures formed by connecting in series stacked Fe-FETs using a multi-stage stacked vertical transistor structure used in a large-capacity stacked NAND memory, an arbitrary reconfigurable combination circuit (2×2 to the power of (half the number of stages) different combinations) of which the outputs are connected at an upper end is realized. Thus, any combinational circuit required for the logic LSI can be realized.SELECTED DRAWING: Figure 1
Inventors:
WATANABE SHIGEYOSHI
Application Number:
JP2018136231A
Publication Date:
January 16, 2020
Filing Date:
July 02, 2018
Export Citation:
Assignee:
WATANABE SHIGEYOSHI
International Classes:
H01L21/82; H01L21/336; H01L27/11556; H01L27/11582; H01L27/11597; H01L29/788; H01L29/792; H03K19/17704