Title:
RECORDING HEAD AND RECORDER EMPLOYING IT
Document Type and Number:
Japanese Patent JP3437423
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To realize a voltage conversion circuit having high noise margin.
SOLUTION: A voltage conversion circuit 131 for enhancing the drivability of an nMOS power transistor is disposed between the gate thereof and the output of a latch circuit 123. The voltage conversion circuit 131 is constituted as a CMOS inverter comprising pMOS transistors 134, 137 for buffer, pMOS transistors 135, 138 and nMOS transistors 136, 139.
Inventors:
Masataka Sakurai
Tatsuo Furukawa
Fumio Murooka
Tatsuo Furukawa
Fumio Murooka
Application Number:
JP30077297A
Publication Date:
August 18, 2003
Filing Date:
October 31, 1997
Export Citation:
Assignee:
Canon Inc
International Classes:
B41J2/175; B41J2/01; B41J2/05; H01L21/8238; H01L27/092; (IPC1-7): B41J2/05; B41J2/01; H01L21/8238; H01L27/092
Domestic Patent References:
| JP1188124A | ||||
| JP10151746A | ||||
| JP6061271A | ||||
| JP59214668A |
Attorney, Agent or Firm:
Yasunori Otsuka (2 outside)