To reduce power consumption of a circuit by cutting design margin included in the circuit designed by a top-down design method.

A branch point of a wiring is detected from layout result (S101), and the delay amount of a path is obtained (S103) both when a dummy buffer is inserted on a wiring in a rear step side from the branch point (S102) and when it is not inserted. An insertion place of a load sharing buffer is decided based on the obtained delay amount (S104). Driving ability of a driving cell positioned in a front step of an insertion place is calculated to satisfy timing constraint under the condition that the load sharing buffer is inserted to the decided insertion place (S105). After checking that the load sharing buffer can be inserted to the decided insertion place (S106), a treatment for disposing the load sharing buffer, a treatment for changing driving ability of the driving cell and a treatment for changing wiring information are carried out to the layout result (S107).