To provide a refreshing method for a semiconductor memory device, which can perform normally a refreshing operation while shortening a memory cell access time.
This method comprises a step (2) for latching a row address for refreshing at the time when refresh request is generated, a step (3) for judging whether a normal operation instruction is inputted from the outside, a step (4) for comparing a block selection bit of a row address for normal operation at the time, with a block selection bit of the latched row address for refreshing, when a normal operation instruction is inputted, and a step (5) for decoding the latched row address for refreshing and activating a word line for refreshing only when the block selection bit of the row address for normal operation is different from the block selection bit of the row address for refreshing in consequence of comparison.
JP2000188539 | SEMICONDUCTOR CIRCUIT |
JPH0713873 | [Title of Invention] Word Line Far End Reset Circuit |
JP2006134469 | SEMICONDUCTOR MEMORY DEVICE |
PARK JONG-YUL
Next Patent: REFRESHING METHOD IN DYNAMIC MEMORY