PURPOSE: To always ensure the resetting with the same timing by setting the reset pulse to the 3rd field regardless of the types of external synchronous signals in case the vertical synchronous signal is synchronized with the external vertical synchronous signal.

CONSTITUTION: Forming circuit 10 of pulse signals SH and SV consists of forming circuit 1 of clock pulse PC, forming circuit 2 of horizontal synchronous pulse signal SH, and forming circuit 3 which forms vertical synchronous pulse signal SV from external composite synchronous signal COP respectively. Thus signals SH and SV plus signal COP are applied to shift registers 21 and 22 of reset pulse forming circuit 20. Then 1st∼3rd shift pulses Pa∼Pc are formed, and then the pulse corresponding to the odd or even field is formed from pulses Pa and Pc. And this pulse plus signal COP or line signal ALT form the specified field pulse, and furthermore the field pulse corresponding to the same field is formed with pulse Pb and burst flag pulse BF. Then reset pulses PR and PR' of the same timing are generated from timing control circuit 25.