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Title:
RESOLUTION CONVERTING CIRCUIT
Document Type and Number:
Japanese Patent JPH05158464
Kind Code:
A
Abstract:

PURPOSE: To perform resolution conversion with a small amount of hardware at a high speed with respect to the resolution conversion required when a display memory differ from the resolution of the display is used.

CONSTITUTION: A display memory 1 with m1×n1 dots is scanned in an X direction synchronously with a clock signal 302 of a frequency f1. The data, which are read from the memory 1 by the scanning, are latched to a register 4 by the clock signal 302. The output of the register 4 is latched to a register 5 by a clock signal 303 of a frequency f2 (f2/f1=m2/m1), and is converted to the X direction resolution of a display 2 with m2×n2 dots. At a read address preparing circuit 31, a Y address with a decimal section is prepared and the integer portion of the address is used as Y address 306 in a read address 304. The Y address with a decimal section is added with an increment n1/n2 at every X direction scanning and updated. Thus, the Y direction of the memory 1 is converted to the Y direction resolution of the display 2.


Inventors:
SANO YOSHINOBU
Application Number:
JP32415691A
Publication Date:
June 25, 1993
Filing Date:
December 09, 1991
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G06T3/40; G09G3/20; G09G5/00; G09G5/36; G09G5/391; G06F3/153; (IPC1-7): G06F3/153; G06F15/66; G09G3/20; G09G5/00; G09G5/36
Attorney, Agent or Firm:
Takehiko Suzue



 
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