Title:
RESTORE CIRCUIT AND ITS STRUCTURE OF SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JP2756437
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent latching-up phenomenon, by installing a feedback means which returns a voltage on an output line to the bias electrode side of a second PMOS transistor.
SOLUTION: When an external power supply voltage Vext increases during operation of a first and a second PMOS transistors Q5, Q6, a feedback loop 60 returns a restore voltage on an output line 65 to the bias electrode side of the second PMOS transistor Q6, via the source and the drain of a third PMOS transistor Q7 and a node 67. When the external power supply voltage Vext increases, the restore voltage on the output line 65 is prevented from being latched up to the internal power supply voltage Vint side. Thereby decrease of driving capability is prevented, and increase of manufacturing process for forming an MOS transistor on an N-type well can be prevented.
Inventors:
RI TOBIN
Application Number:
JP35504595A
Publication Date:
May 25, 1998
Filing Date:
December 28, 1995
Export Citation:
Assignee:
GENDAI DENSHI SANGYO KK
International Classes:
G11C11/413; G11C5/14; G11C11/407; G11C11/4074; G11C11/409; H01L21/8238; H01L21/8242; H01L27/092; H01L27/108; (IPC1-7): H01L27/108; G11C11/409; H01L21/8242
Domestic Patent References:
| JP271492A |
Attorney, Agent or Firm:
Yoshiki Hasegawa (3 outside)