PURPOSE: To operate a counter circuit at a high speed at a frequency close to a limit when a flip-flop single device is in operation regardless of the load of a decoder.

CONSTITUTION: The ripple counter is configured by connecting the Q output of a pre-stage flip-flop to the clock terminal of a succeeding-stage flip-flop in flip-flop circuits 11-15 implementing toggle operation in which each XQ output is connected to a D input. Furthermore, output additional flip-flop circuits 21-25 whose inputs are formed to be entirely the same as those of the flip-flop circuits 11-15 are provided respectively on the flip-flop circuits 11-15, and an output additional flip-flop 31 whose input is configured the same as that of the flip-flop circuits 11, 12 is provided on a 1st stage flip-flop 11 and the output additional flip-flop 31. Then Q outputs of the output additional flip-flop circuits 21-25, 31 are inputted to decoders 41, 42 and the result is latched by flip-flop circuits 51, 52.