PURPOSE: To always obtain a correct output by using an addition circuit group which adds together the data stored in three ROMs of the same type for each bit and an arithmetic processing circuit which inputs the data group of the addition result 21 as the data.

CONSTITUTION: When an arithmetic processing circuit 6 instructs the output of data stored in ROM 1W3 via an address bus 8, these ROM 1W3 deliver their data to data lines 5-1W5-3. These data are inputted to an addition circuit 4. In this case, the data on '1' and '0' are inputted to the circuit 6 via a data line 9 as a single bit of the data when the data on the addition result 21 is equal to ≥2 and 1 respectively. In such a way, the correct storing data is obtained despite and trouble of either one of those RAM 1W3 by adding together the data stored in the ROM 1W3. For instance, the data on the result 21 is equal to 0 even when the ROM 1 has a trouble and is equal to (1, 0, 0) with storing bits of the ROM 1W3 equal to (0, 0, 0). Thus the output of the correct data bits is secured for the circuit 6.