Title:
RUN LENGTH DETECTING CIRCUIT
Document Type and Number:
Japanese Patent JPS6439169
Kind Code:
A
Abstract:
PURPOSE:To reduce hardware load and increase detecting speed with a run length detecting circuit by providing an input register, a multiplexer, a barrel shifter, a buffer/inverter circuit, a priority encoder, a shift counter and a run length detector. CONSTITUTION:An input register 101 inputs a first (n) bits of the picture data to a #1 register and the following (n) bits to a #2 register respectively. A multiplexer 102 outputs 2n bits with #1 and #2 set at the lower level side and the higher level side respectively. A barrel shifter 103 shifts data toward the LSB side by an extent equal to the value of a shift counter 106 Priority encoder 105 detects the position of the bit that changed first into 1 in the direction toward the highest level bit from the lowest level bit and output said bit position as the information on a changing point. A buffer/inverter circuit 104 has the switch of its actions when said changing point information is smaller than (n). Then the counter 106 performs the addition and the subtraction of the changing point information to the held data and decides the shift value. A run length integrator 107 applies the addition to the held data when the changing point information is smaller than (n) and outputs the result of this addition as the run length.
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Inventors:
NINOMIYA YUKO
Application Number:
JP19557787A
Publication Date:
February 09, 1989
Filing Date:
August 04, 1987
Export Citation:
Assignee:
NEC CORP
International Classes:
H04N1/419; G06T9/00; (IPC1-7): G06F15/66; H04N1/419
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)