Title:
SAMPLE-AND-HOLD AMPLIFIER CIRCUIT AND DATA CONVERTER OF PARALLEL PIPELINE TYPE
Document Type and Number:
Japanese Patent JP2002190736
Kind Code:
A
Abstract:
To reduce power consumption.
The first and second sampling circuits for sampling an input signal and an arithmetic amplifier for performing the arithmetic amplification of an input signal sampled by these sampling circuit are provided. The arithmetic amplifier is provided with an arithmetic amplifying state 11 connected to the first sampling circuit, an arithmetic amplifying state 12 connected to the second sampling circuit, a single arithmetic amplifying stage 13 provided at the post stages of the first and second prestage amplifying stage 11 and 12, and a switch 27 for switching the connection of the output sides of the stages 11 and 12 to the input side off this stage 13 between the output side of the stage 11 and that of the stage 12.
Inventors:
FUJIMOTO YOSHIHISA
Application Number:
JP2000389513A
Publication Date:
July 05, 2002
Filing Date:
December 21, 2000
Export Citation:
Assignee:
SHARP KK
International Classes:
G11C27/02; H03M1/14; H03M1/72; H03M9/00; (IPC1-7): H03M1/14; G11C27/02; H03M1/72; H03M9/00
Attorney, Agent or Firm:
Kenzo Hara