To provide a semiconductor integrated circuit for accurately and speedily synchronizing signals.

The semiconductor integrated circuit for detecting the phase shifting of a clock signal CK and a data signal Data is provided with delay circuits 1, 2 for generating plural judging reference period signals of different phases by shifting the phase of the supplied clock signal CK, phase judging circuits 3 and 4 for detecting the phase shifting between the clock signal CK and the data signal Data by comparing the mutual logical level of the respective judging reference period signals and the data signal Data, and a lock state judging circuit 5 for generating LK/ULK showing a phase state in accordance with the phase shifting detected by the circuits 3 and 4.