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Title:
SAMPLE-AND-HOLD CIRCUIT
Document Type and Number:
Japanese Patent JPH08222966
Kind Code:
A
Abstract:

PURPOSE: To operate the sample-and-hold operation with high accuracy by providing a means applying a potential of an input signal to a hold capacitor, transistors(TRs) in emitter follower operation, an amplifier and a means supplying a base current to the TRs to the sample-and-hold circuit.

CONSTITUTION: When a clock signal 14 is at an H level and an inverted clock signal 12 is at an L level, an input level of an analog signal charges up a hold capacitor 11. Since a current of a constant current source 344 of a differential amplifier 301 flows to a TR 341, an emitter current of a TR 215 and an emitter current of a 341 in a leakage current compensation circuit 201 are made equal to each other. The current 14 is supplied to a current mirror circuit, then a current 15 nearly equal to the current 14 is outputted to a terminal 241 and fed to a base of the TR 341. As a result, a leakage current from a capacitor 11 by a base current of the TR 341 is compensated by a current from the circuit 201 and then the sample-and-hold circuit is operated with high accuracy.


Inventors:
HIRANO YOJI
UEDA GORO
Application Number:
JP2504595A
Publication Date:
August 30, 1996
Filing Date:
February 14, 1995
Export Citation:
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Assignee:
NEC CORP
International Classes:
G11C27/02; H03F3/04; H03M1/12; (IPC1-7): H03F3/04; G11C27/02; H03M1/12
Domestic Patent References:
JPH04172700A1992-06-19
JPH04330507A1992-11-18
JPS61283279A1986-12-13
JPH05217395A1993-08-27
JPS545366A1979-01-16
JPH0479407A1992-03-12
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
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