PURPOSE: To reduce the number of circuit elements by providing a means which is so connected that delay signals are successively supplied to a first input terminal group in the descending order of the extent of delay and is supplied to a second input terminal group in the ascending order of the extent of delay.

CONSTITUTION: A signal train is led to an input terminal 11 and supplied to a unit delay element 3 and a coefficient device 21 of a filter 23. Unit delay elements 3 to 6 are connected in series and driven by the clock inputted from a terminal 2. Delayed digital signals are inputted to one input terminals of selective circuits 7 to 9 in the descending order of the delay time and are inputted to the other input terminals in the ascending order of the delay time. Thus, at least adders and coefficient devices of two interpolating filters can be shared, and the hardware scale of the circuit is reduced.