To lower the manufacturing cost of a sampling rate converter.

The sampling rate converter is provided with a buffer (203) which captures input data, a sampling rate converter core (201) for converting the sampling rate of its output data, and a sampling rate conversion control section (202) which can control sampling conversion of the sampling rate converter core. The sampling rate conversion control section includes a table (205) of control information regarding the sampling rate conversion of the sampling rate converter core and a sampling rate arithmetic module (204) which refers to it to find an input sampling rate of the sampling rate converter core, and enables the control information in the table to be rewritten. The need for a PLL circuit for sampling rate conversion is eliminated and the manufacturing cost of the sampling rate converter is reduced.