To provide a scan converting circuit which is adaptive to various input image signals, small in number of set data for adaptation to display devices having various numbers of pixels, and small in circuit scale.
A coefficient setting part 101 of the scan converting circuit sets calculation coefficients etc., for a long period and a short period (an initial term (a) and a tolerance (d) for finding a general term of an arithmetic progression), and a long period calculation part 102 and a short period calculation part 103 generate clock signals LCK and SCK having been thinned out except clock pulses in the order corresponding to the general term. Then a clock signal converting part 104 generates a conversion clock signal MCK by putting those clock signals together and then an image signal conversion part 105 obtains an output image signal Dout having been thinned out between pixel data of an input image signal Din according to the conversion clock signal MCK, so the number of set data is decreased and the circuit can be simplified.
JPH07129117A | 1995-05-19 | |||
JP2004046161A | 2004-02-12 |
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