To execute a scan test even in a circuit including a block not allowing the scan test such as a memory.

In this scan test circuit, a scan control signal S119nt is set to 'L' and data are set to scan flip-flops 110, 111. The scan test circuit has selectors 115, 116 into which output signals S114a, S114b of a memory 114 and data S110, S111 can be inputted. When a scan test is executed, the data S110, S111 are selected with a selection signal al S119s. The scan control signal S119nt is set to 'H' and a normal operation is executed for one clock period, while data passing an AND circuit 117 and an OR circuit 118 are set to scan flip-flops 113, 112. Then, the scan control signal S119nt is set to 'L', and the data set to the scan flip-flops 113, 112 are taken out as scan data S113.